An LFSR is a shift register that, when clocked, advances the signal through the register from one bit to the next most-significant bit. Present semiconductor manufacturing industries are involved in various challenges in reducing test data volume and its corresponding transition time. Keywords: Test data volume, Transition Time, Area overhead, Liner Feedback Shift Register, and TapĪ'b'cSchool of Computing (SoC), SASTRA University, Thanjavar, Tamilnadu -613 401, INDIA dM.Tech VLSI Design, SoC, SASTRA University, Thanjavur, Tamilnadu - 613 401, INDIAġ877-7058 © 2012 Published by Elsevier Ltd. Selection and/or peer-review under responsibility of Noorul Islam Centre for Higher Education Experimental result shows significant reduction in test data volume, area and transition time. This proposed method is targeted to XILINX Virtex-6 FPGA. This proposed approach is based on considering various taps associated with Slow LFSR and Normal LFSR modules. Using the advantages of LFSR in producing pseudorandom pattern, it is considered for SoC testing. This paper considers Linear Feedback Shift Register (LFSR) with various tap to address the above problem.

This huge test data volume and its transition time is becoming one of the major problems in association with SoC design testing. Systems-on-Chip (SoC) based design rapidly involves various challenges like huge test data volume, test transition time, area overhead and test data storage.

International Conference on Modeling, Optimization and Computingĭesign and Analysis of Linear Feedback Shift Register based

Available online at Procedía Engineering

Taps for linear feedback shift register